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| K5P2880YCM - T085 Document Title Multi-Chip Package MEMORY 128M Bit (16Mx8) Nand Flash Memory / 8M Bit (1Mx8/512Kx16) Full CMOS SRAM Revision History Revision No. History 0.0 Initial issue. Draft Date Jun. 11th 2001 Remark Advanced Information Note : For more detailed features and specifications including FAQ, please refer to Samsung' web site. s http://samsungelectronics.com/semiconductors/products/products_index.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. -1- Revision 0.0 June. 2001 K5P2880YCM - T085 Multi-Chip Package MEMORY 128M Bit (16Mx8) Nand Flash Memory / 8M Bit (1Mx8/512Kx16) Full CMOS SRAM FEATURES * Power Supply voltage : 2.7V to 3.3 V * Organization - Flash : (16M + 512K)bit x 8bit - SRAM : 1M x 8 / 512K x 16 bit * Access Time - Flash : Random access : 10us(Max.), Serial read : 50ns(Min.) - SRAM : 85 ns * Power Consumption (typical value) - Flash Read Current : 10 mA(@20MHz) Program/Erase Current : 10 mA Standby Current : 10 A - SRAM Operating Current : 20 mA Standby Current : 0.5 A * Flash Automatic Program and Erase Page Program : (512 + 16)Byte Block Erase : (16K + 512)Byte * Flash Fast Write Cycle Time Program time : 300us(Typ.) Block Erase Time : 2ms(Typ.) * Flash Endurance : 100,000 Program/Erase Cycles Minimum * Flash Data Retention : 10 years * SRAM Data Retention : 1.5 V (min.) * Operating Temperature : -25C ~ 85C * Package : 69 - ball TBGA Type - 8 x 13mm, 0.8 mm pitch GENERAL DESCRIPTION The K5P2880YCM featuring single 3.0V power supply is a Multi ChipPackage Memory which combines 128Mbit Nand Flash and 8Mbit full CMOS SRAM. The 128Mbit Flash memory is organized as 16M x8 bit and the 8Mbit SRAM is organized as 1M x8 or 512K x16 bit. In 128Mb NAND Flash a 528-byte page program can be typically achieved within 300us and an 16K-byte block erase can be typically achieved within 2ms. In serial read operation, a byte can be read by 50ns. The I/O pins serve as the ports for address and data input/output as well as command inputs. Even the write-intensive systems can take advantage of the FLASHs extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ECC. The 8Mbit SRAM supports the low data retention voltage for battery backup operation with low current. The K5P2880YCM is suitable for use in data memory of mobil communication system to reduce not only mount area but also power consumption. This device is available in 69-ball TBGA Type. BALL CONFIGURATION 1 A B C D E F G H J K N.C N.C N.C N.C LB BALL DESCRIPTION Ball Name Description Address Input Balls (SRAM) Data Input/Output Balls (Common) Data Input/Output Balls (SRAM) Power Supply (SRAM) Power Supply (Flash Memory) Output Buffer Power (Flash Memory) This input may be tied directly to VCCF. Ground (Common) Upper Byte Enable (SRAM) Lower Byte Enable (SRAM) Write Protection (Flash Memory) Command Latch Enable(Flash Memory) Address Latch Enable(Flash Memory) Byte Control (SRAM) Address Inputs (SRAM) Chip Enable (Flash Memory) Chip Enable (SRAM Low Active) Chip Enable (SRAM High Active) Write Enable (Common) Output Enable (Common) Ready/Busy (Flash memory) No Connection 2 3 4 5 N.C 6 N.C 7 8 9 10 N.C A0 to A18 D/Q0 to D/Q7 D/Q8 to D/Q15 Vccs VccF Index A3 A2 A1 A0 WP CS1s A7 CLE WE CS2s N.C A8 A11 A6 A5 UB A18 A17 DQ1 CEf ALE N.C A9 A12 A13 A14 SA A15 N.C VccQF Vss A4 VSS OE/RE DQ0 DQ8 A10 DQ6 DQ3 VccQF DQ11 N.C DQ4 VccS BYTES N.C DQ13 DQ12 DQ5 Vccf A16 R/B Vss N.C N.C UB LB WP CLE ALE DQ9 DQ10 DQ2 DQ15 DQ7 DQ14 BYTES SA CEF N.C CS1S CS2S WE 69 Ball TBGA , 0.8mm Pitch Top View (Ball Down) OE/RE R/B N.C SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2- Revision 0.0 June. 2001 K5P2880YCM - T085 Figure 1. FUNCTIONAL BLOCK DIAGRAM Vccf Vss VccQf WP CEf CLE ALE OE/RE WE R/B 128 M bit Flash Memory DQ0 to DQ7 Vccs Vss DQ0 to DQ15 Address(A0 to A18) SA UB LB BYTES CS1S CS2S 8 M bit Static RAM DQ0 to DQ15 Figure 2. Flash ARRAY ORGANIZATION 1 Block =32 Pages = (16K + 512) Bytes 32K Pages (=1024 Blocks) 1st half Page Register (=256 Bytes) 2nd half Page Register (=256 Bytes) 1 Page = 528 Bytes 1 Block = 528 Bytes x 32 Pages = (16K + 512) Bytes 1 Device = 528 Bytes x 32Pages x 1024 Blocks = 132 Mbits 8 bit 16 Bytes 512Bytes Page Register 512 Bytes I/O 0 ~ I/O 7 16 Bytes I/O 0 1st Cycle 2nd Cycle 3rd Cycle A0 A9 A17 I/O 1 A1 A10 A18 I/O 2 A2 A11 A19 I/O 3 A3 A12 A20 I/O 4 A4 A13 A21 I/O 5 A5 A14 A22 I/O 6 A6 A15 A23 I/O 7 A7 A16 *L Column Address Row Address (Page Address) NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low" -3- Revision 0.0 June. 2001 K5P2880YCM - T085 NAND FLASH PRODUCT INTRODUCTION The NAND Flash is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare 16 columns are located in 512 to 527 column address. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected like NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by one NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. Program and read operations are executed on a page basis, while erase operation is executed on a block basis. The memory array consists of 1024 blocks, and a block is separately erasable by 16K-byte unit. It indicates that the bit by bit erase operation is prohibited on the NAND Flash. The NAND Flash has addresses multiplexed with 8 I/Os. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/Os by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except Page Program command and Block Erase command which require two cycles: one cycle for setup and another for execution. The 16M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following required command input. In Block Erase operation, however, only two row address cycles are used. Device operations are selected by writing specific commands into command register. Table 1 defines the specific commands of the NAND Flash. Table 1. COMMAND SETS Function Read 1 Read 2 Read ID Reset Page Program Block Erase Read Status 1st. Cycle 00h/01h(1) 50h 90h FFh 80h 60h 70h 2nd. Cycle 10h D0h O O Acceptable Command during Busy NOTE : 1. The 00h command defines starting address of the 1st half of registers. The 01h command defines starting address of the 2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. -4- Revision 0.0 June. 2001 K5P2880YCM - T085 Table 2. FLASH MEMORY OPERATIONS TABLE CLE H L H L L L L X X X X ALE L H L H L L L X X X(1) X CE L L L L L L X X X X H H H X X X X H X X X X WE RE H H H H H WP X X H H H X X H H L Read Mode Mode Command Input Address Input(3clock) Command Input Address Input(3clock) Write Mode Data Input Sequential Read & Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect 0V/VCC(2) Stand-by NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. Table 3. SRAM OPERATIONS TABLE 1. Word Mode CS1 H X X L L L L L L L L CS2 X L X H H H H H H H H OE X X X H H L L L X X X WE X X X H H H H H L L L BYTE X X X VCC VCC VCC VCC VCC VCC VCC VCC SA X X X X X X X X X X X LB X X H L X L H L L H L UB X X H X L H L L H L L I/O0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active Note: X means dont care. (Must be low or high state) 2. Byte Mode CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L BYTE X X VSS VSS VSS SA X X SA 1) LB X X DNU DNU DNU UB X X DNU DNU DNU I/O0~7 High-Z High-Z High-Z Dout Din I/O8~15 High-Z High-Z DNU DNU DNU Mode Deselected Deselected Output Disabled Lower Byte Read Lower Byte Write Power Standby Standby Active Active Active SA1) SA 1) Note: X means dont care.(Must be low or high state) 1. Address input for byte operation. -5- Revision 0.0 June. 2001 K5P2880YCM - T085 FLASH MEMORY OPERATION PAGE READ Upon initial device power up, the device status is initially Read1 command(00h) latched. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operation are available : random read, serial page read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 10s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out by sequential RE pulse of 50ns period cycle. High to low transitions of the RE clock take out the data from the selected column address up to the last column address. Read1 and Read2 commands determine pointer which selects either main area or spare area. The spare area(512 to 527 bytes) may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of spare area while addresses A4 to A7 are ignored. To move the pointer back to the main area, Read1 command(00h/01h) is needed. Figures 3 through 4 show typical sequence and timing for each read operation. Figure 3,4 details the sequence. Figure 3. Read1 Operation CLE CE WE ALE tR R/B RE I/O0 ~ 7 00h 01h Start Add.(3Cycle) A0 ~ A7 & A9 ~ A23 Data Output(Sequential) (00h Command) 1st half array 2nd half array (01h Command)* 1st half array 2nd half array Data Field Spare Field Data Field Spare Field * After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00h) at next cycle. -6- Revision 0.0 June. 2001 K5P2880YCM - T085 Figure 4. Read2 Operation CLE CE WE ALE tR R/B RE I/O0 ~ 7 50h Start Add.(3Cycle) Data Output(Sequential) Spare Field 1st half array 2nd half array A0 ~ A3 & A9 ~ A23 (A4 ~ A7 : Don't Care) Data Field Spare Field PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state-control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 5). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 5. Program & Read Status Operation tPROG R/B I/O0 ~ 7 80h Address & Data Input A0 ~ A7 & A9 ~ A23 528 Byte Data 10h 70h I/O0 Pass Fail -7- Revision 0.0 June. 2001 K5P2880YCM - T085 BLOCK ERASE The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A14 to A23 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write state-control handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 6 details the sequence. Figure 6. Block Erase Operation tBERS R/B I/O0 ~ 7 60h Address Input(2Cycle) Block Add. : A9 ~ A23 D0h 70h I/O0 Pass Fail READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. Table4. Read Status Register Definition I/O # I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Device Operation Write Protect Reserved for Future Use Status Program / Erase Definition "0" : Successful Program / Erase "1" : Error in Program / Erase "0" "0" "0" "0" "0" "0" : Busy "0" : Protected "1" : Ready "1" : Not Protected -8- Revision 0.0 June. 2001 K5P2880YCM - T085 READ ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (73h) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 7 shows the operation sequence. Figure 7. Read ID Operation CLE tCEA CE WE tAR1 ALE tWHR RE I/O0~7 tREA 00h Address. 1cycle ECh Maker code 90h 73h Device code RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to "1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 8 below. Figure 8. RESET Operation tRST R/B I/O0 ~ 7 FFh Table5. Device Status After Power-up Operation Mode Read 1 After Reset Waiting for next command -9- Revision 0.0 June. 2001 K5P2880YCM - T085 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper operation and the value may be calculated by the following equation. Rp VCC VCC(Max.) - VOL(Max.) R/B open drain output Rp = IOL + IL = 2.9V 8mA + IL where IL is the sum of the input currents of all devices tied to the R/B pin. GND Device DATA PROTECTION The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down as shown in Figure 9. The two step command sequence for program/erase provides additional software protection. Figure 9. AC Waveforms for Power Transition ~ 2.2V ~ 2.2V VCC WP High - 10 - Revision 0.0 June. 2001 K5P2880YCM - T085 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to be a valid block. Identifying Invalid Block(s) All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 10). Any intentional erasure of the original invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address Check "FFh" at the column address 517 of the 1st and 2nd page in the block Create (or update) Invalid Block(s) Table No Check "FFh" ? * Yes No Last Block ? Yes End Figure 10. Flow chart to create invalid block table - 11 - Revision 0.0 June. 2001 K5P2880YCM - T085 Error in write or read operation Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks. Failure Mode Erase Failure Write Program Failure Single Bit Failure Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement or ECC Correction Verify ECC -> ECC Correction Read ECC : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection Figure 11. Flash Program flow chart If ECC is used, this verification operation is not needed. Start Write 00h Write 80h Write Address Write Address Write Data Wait for tR Time Write 10h Verify Data No * Program Error Read Status Registe Yes Program Completed I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? No * * Program Error : If program operation results in an error, map out the block including the page in error and copy the target data to another block. Yes - 12 - Revision 0.0 June. 2001 K5P2880YCM - T085 Figure 12. Flash Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register Figure 13. Flash Read Flow Chart Start Write 00h Write Address Read Data ECC Generation I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Erase Completed No Reclaim the Error No Verify ECC Yes Page Read Completed * Erase Error * : If erase operation results in an error, map out the failing block and replace it with another block. Figure 14. Flash Block Replacement Buffer memory error occurs Page a Block A When the error happens with page "a" of Block "A", try to write the data into another Block "B" from an external buffer. Then, prevent further system access to Block "A" (by creating a "invalid block" table or other appropriate scheme.) Block B - 13 - Revision 0.0 June. 2001 K5P2880YCM - T085 Pointer Operation of NAND Flash The Flash memory has three modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B" area by the "01h" command, and to "C" area by the "50h" command. Table 6 shows the destination of the pointer, and figure 15 shows the block diagram of its operations. "A" area (00h plane) "B" area (01h plane) 256 Byte "C" area (50h plane) 16 Byte Table 6. Destination of the pointer Command 00h 01h 50h Pointer position 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte Area 1st half array(A) 2nd half array(B) spare array(C) 256 Byte "A" "B" "C" Internal Page Register Pointer select commnad (00h, 01h, 50h) Pointer Figure 15. Block Diagram of Pointer Operation Example of Programming with successive Pointer Operation (1) "A" area program 50h "C" area 00h "A" area 80h Address / Data input 10h "A" area program 80h Address / Data input 10h "A" area program (2) "B" area program 00h "A" area 01h "B" area 80h Address / Data input 10h "B" area program 80h Address / Data input 10h "A" area program (3) "C" area program 00h "A" area 50h "C" area 80h Address / Data input 10h "C" area program 80h Address / Data input 10h "C" area program Table 7. Pointer Status after each operation Operation Program Pointer status after operation With previous 00h, Device is set to 00h Plane With previous 01h, Device is set to 00h Plane* With previous 50h, Device is set to 50h Plane "00h" Plane("A" area) "00h" Plane("A" area) Reset Power up * 01h command is valid just one time when it is used as a pointer for program/erase. * Erase operation does not affect the pointer status. Previous pointer status is maintained. - 14 - Revision 0.0 June. 2001 K5P2880YCM - T085 System Interface Using CE don' -care. t For an easier system interface, CE may be inactive during data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant saving in power consumption. Figure 16. Program Operation with CE don' -care. t CLE CE don'-care t CE WE ALE I/O0~7 80h Start Add.(3Cycle) Data Input Data Input 10h (Min. 10ns) tCS CE (Max. 45ns) tCH CE tCEA tREA tWP WE I/O0~7 out RE t Figure 17. Read Operation with CE don' -care. CLE CE don'-care t CE RE ALE R/B tR WE I/O0~7 00h Start Add.(3Cycle) Data Output(sequential) - 15 - Revision 0.0 June. 2001 K5P2880YCM - T085 ABSOLUTE MAXIMUM RATINGS Parameter Symbol VIN Voltage on any pin relative to VSS VCCf, VCCs VccQ Temperature Under Bias Storage Temperature TBIAS TSTG Rating -0.5 to (Vccf,Vccs)+ 0.3 -0.2 to 3.6V -0.2 to 3.6V -25 to + 125 -65 to + 150 Unit V V C C NOTE : 1. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, TA=-25 to 85C) Parameter Supply Voltage Supply Voltage Supply Voltage Symbol VCCf, VCCs VCCQ VSS Min 2.7 2.7 0 Typ. 3.0 3.0 0 Max 3.3 3.3 0 Unit V V V DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) Parameter Input Leakage Current Output Leakage Current Input Low Voltage Level, All inputs Input High Voltage Level Output Low Voltage Level Symbol ILI ILO VIL VIH VOL VOH Vccf/=Vccf Min, Vccs=Vccs Min IOL = 0.1mA Vccf=Vccf Min, Vccs=Vccs Min. IOH = -0.1mA Test Conditions VCCf,VCCS=VCCfMax.,VCCSMax. VCCQf=VCCQfMax.,VIN=VCCQf or GND VCCf,VCCS=VCCfMax.,VCCSMax. VCCQf=VCCQfMax.,VIN=VCCQf or GND Min -0.4 VccQf-0.4 VccQ-0.3 Max 10 10 0.4 VccQf+0.4 0.4 V Unit A A Output High Voltage Level - 16 - Revision 0.0 June. 2001 K5P2880YCM - T085 DC AND OPERATING CHARACTERISTICS(Continued) Parameter Active Sequential Read Currnt Flash Active Program Current Active Erase Current Stand_by Current Symbol ICC1f ICC2f ICC3f ISB2f ICC1s Operating Current SRAM ICC2s Test Conditions tRC=50ns,CEf=VIL, IOUT=0mA VCCf=VCCfMax,VCCQf=VCCQfMax VCCf=VCCfMax,VCCQf=VCCQfMax VCCf=VCCfMax,VCCQf=VCCQfMax CEf=VccQf, WP=0V/VCCQf Cycle time=1s, 100% duty, CS1s0.2V, CS2sVccS-0.2V, All outputs open VIN0.2V or VINVCCS-0.2V Cycle time=Min, 100% duty, CS1s=VIL, CS2s=VIH All outputs open, VIN=VIL or VIH CS1sVccS-0.2V, CS2sVccS-0.2V (CS1s controlled) or CS2s0.2V (CS2s controlled), BYTES=VSS or VCCS Other input =0~VccS Typ 10 10 10 10 Max 20 20 20 50 5 Unit mA mA mA A mA 30 mA Stand_by Current(CMOS) ISB2s 15 A CAPACITANCE (TA = 25 C, VCC = 3.0V, f = 1.0MHz) Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 20 18 Unit pF pF Note : Capacitance is periodically sampled and not 100% tested. VALID BLOCK OF FLASH MEMORY Parameter Valid Block Number Symbol NVB Min 1014 Typ. 1020 Max 1024 Unit Blocks NOTE : 1. The Flash memory may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block. - 17 - Revision 0.0 June. 2001 K5P2880YCM - T085 AC TEST CONDITION Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Value 0V to VccQf 5ns VccQf/2 1TTL gate and CL = 50pF Note : AC test inputs are driven at VccQ for a logic "1" and 0.0V for a logic "0". Input timing begins, and output timing ends, at VccQ / 2. Input rise and fall times (10% - 90%)<5ns. Worst case speed condition are when VccQf = VccQf Min. VccQf VccQf 2 0V Input & Output Test Point VccQf 2 Input Pulse and Test Point VccQ 25K Device Under Test CL 25K Out - 18 - Revision 0.0 June. 2001 K5P2880YCM - T085 Flash Program/Erase Characteristics Parameter Program Time Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol tPROG Nop tBERS Min Typ 300 2 Max 600 2 3 4 Unit s cycles cycles ms Flash AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 0 10 0 10 25 0 10 20 10 50 15 Max Unit ns ns ns ns ns ns ns ns ns ns ns Flash AC Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE Delay( ID read ) ALE to RE Delay(Read cycle) CE Access Time Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High Hold Time Output Hi-Z to RE Low WE High to RE Low Device Resetting Time(Read/Program/Erase) NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us Symbol tR tAR1 tAR2 tCEA tRR tRP tWB tRC tREA tRHZ tCHZ tREH tIR tWHR tRST Min 20 50 20 30 50 15 15 0 60 - Max 10 45 100 35 30 20 5/10/500 (1) Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns s - 19 - Revision 0.0 June. 2001 K5P2880YCM - T085 * Command Latch Cycle CLE tCLS tCS CE tCLH tCH tWP WE tALS ALE tDS I/O0~7 tALH tDH Command * Address Latch Cycle tCLS CLE tCS CE tWC tWC tWP WE tALS ALE tDS tDH tWH tALH tALS tWP tWH tALH tALS tWP tALH tDS tDH tDS tDH I/O0~7 A0~A7 A9~A16 A17~A23 - 20 - Revision 0.0 June. 2001 K5P2880YCM - T085 * Input Data Latch Cycle tCLH CLE tCH CE tALS ALE tWC tWP WE tDS I/O0~7 tWH tDH tWP tDH tWP tDH tDS tDS DIN 0 DIN 1 DIN 511 * Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L) tREH RE tRHZ* CE tRC tCHZ* tREA tREA tREA tRHZ* I/O0~7 tRR R/B Dout Dout Dout NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. - 21 - Revision 0.0 June. 2001 K5P2880YCM - T085 * Status Read Cycle tCLS CLE tCLS tCS CE tCH tWP WE tWHR RE tDS I/O0~7 70h tDH tIR tREA tRHZ Status Output tCEA tCHZ tCLH READ1 OPERATION(READ ONE PAGE) CLE CE tWC WE tWB tAR2 ALE tR RE tRR I/O0~7 00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A23 Dout N Dout N+1 Dout N+2 Dout N+3 tCHZ tRC tRHZ Dout 527 Column Address Page(Row) Address Busy R/B - 22 - Revision 0.0 June. 2001 K5P2880YCM - T085 READ2 OPERATION(READ ONE PAGE) CLE CE WE tWB tR tAR2 ALE tRR I/O0 ~ 7 50h A0 ~ A7 A9 ~ A16 A17 ~ A23 Dout 511+M Dout 511+M+1 RE Dout 527 R/B M Address A0 ~ A3 :Valid Address A4 ~ A7 :Dont care Selected Row 512 16 Start address M PAGE PROGRAM OPERATION CLE CE tWC WE tWB ALE tPROG tWC tWC RE Din Din Din 10h 527 N N+1 1 up to 528 Byte Data Program Sequential Input Command I/O0 ~ 7 80h A0 ~ A7 A9 ~ A16 A17 ~ A23 Page(Row) Address 70h Read Status Command I/O0 Sequential Data Column Input Command Address R/B I/O0=0 Successful Program I/O0=1 Error in Program - 23 - Revision 0.0 June. 2001 K5P2880YCM - T085 BLOCK ERASE OPERATION(ERASE ONE BLOCK) CLE CE tWC WE tWB ALE tBERS RE I/O0~7 60h A9 ~ A16 A17 ~ A23 Page(Row) Address DOh 70h I/O 0 R/B Auto Block Erase Setup Command Erase Command Busy Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE tREA I/O0 ~ 7 90h Read ID Command 00h Address 1st Cycle ECh Maker Code 73h Device Code - 24 - Revision 0.0 June. 2001 K5P2880YCM - T085 SRAM AC CHARACTERISTICS Parameter List Read cycle time Address access time Chip select to output Output enable to valid output UB, LB Access Time Read Chip select to low-Z output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write UB, LB Valid to End of Write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z Symbol Min tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 85 10 10 5 0 0 0 15 85 70 0 70 70 60 0 0 35 0 5 85ns Max 85 85 45 85 25 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units SRAM DATA RETENTION CHARACTERISTICS Item Vccs for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1sVccs-0.2V 1) Min 1.5 25 C 85 C 0 tRC Typ 2.0 2) - Max 3.3 5 25 - Unit V A Vccs=3.0V, CS1sVccs-0.2V 1) See data retention waveform ns 1. CS1sVccs-0.2V, CS2sVccs-0.2V(CS1s controlled) or CS2s0.2V(CS2s controlled), BYTE=Vss or Vcc. 2. Typical values are not 100% tested - 25 - Revision 0.0 June. 2001 K5P2880YCM - T085 SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1S=OE=VIL, CS2S=WE=VIH, UB or/and LB=VIL) tRC Address tOH Data Out Previous Data Valid tAA Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH , if CIOs is low, ignore UB/LB timing) tRC Address tAA tCO1 tOH CS1S CS2S tCO2 tHZ UB, LB tBA tBHZ OE tOLZ tBLZ tLZ Data Valid tOE tOHZ Data out High-Z NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. - 26 - Revision 0.0 June. 2001 K5P2880YCM - T085 SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled, if CIOs is low, ignore UB/LB timing) tWC Address tCW(2) CS1S tAW CS2S tCW(2) tBW tWP(1) WE tAS(3) tDW Data in High-Z tWHZ Data out Data Undefined Data Valid tOW tDH High-Z tWR(4) UB, LB TIMING WAVEFORM OF WRITE CYCLE(2) (CS1S Controlled, if CIOs is low, ignore UB/LB timing) tWC Address tAS(3) CS1S tAW CS2S tBW UB, LB tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z - 27 - Revision 0.0 June. 2001 K5P2880YCM - T085 TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled, CIOs must be high.) tWC Address tCW(2) CS1S tAW CS2S UB, LB tCW(2) tBW tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4) Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap(tWP) of low CS1S and low WE. A write begins when CS1S goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1S goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1S going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1S or WE going high. SRAM DATA RETENTION WAVE FORM CS1S controlled VCCS 2.4V tSDR Data Retention Mode tRDR 2.2V VDR CS1SVCCS - 0.2V CS1S GND CS2S controlled VCCS 2.4V CS2S tSDR Data Retention Mode tRDR VDR 0.4V GND CS2S0.2V - 28 - Revision 0.0 June. 2001 K5P2880YCM - T085 PACKAGE DIMENSION 69-Ball Tape Ball Grid Array Package (measured in millimeters) Top View Bottom View 8.000.10 0.80 x9=7.20 A A1 INDEX MARK 3 2 1 B 8.000.10 (Datum A) 10 9 8 7 6 0.80 5 4 A (Datum B) #A1 13.000.10 B C 0.80x9=7.20 D E F 3.60 G H J K 0.80 13.000.10 1.100.10 3.60 69- 0.450.05 0.20 M A B Side View 0.450.05 0.350.05 13.000.10 0.08MAX - 29 - Revision 0.0 June. 2001 |
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